This invention generally relates to an alignment technique, and, more particularly to a method of aligning patterned layers in an integrated circuit or other device and a device formed thereby, to a method of adjusting the alignment of patterned layers in an integrated circuit or other device, and to an apparatus therefor.
The fabrication of integrated circuits and other electronic circuits on wafers is a precise process which results in a precisely constructed circuit. However, as with any manufacturing process, there is some variation in the fabrication process which may be manifested in the manufactured circuit. A functional circuit results when the variation is within acceptable tolerances and a defective circuit results when the variation is beyond acceptable tolerances.
One such tolerance is related to the relative alignment between layers in the circuit. The circuit components of one layer must be aligned within acceptable tolerances to the circuit components in one or more associated layers in order to interact as required. Thus, metrology marks such as an X pattern or a xe2x96xa1 (square) pattern have been employed to assure the alignment of associated layers is within acceptable tolerances. Unfortunately, tolerances become smaller as circuit line widths become smaller.
The decreased line widths of modern circuits have resulted in tolerances so small that conventional metrology alignment techniques no longer insure proper alignment between layers. This can be attributed to several problems. For example, the optical alignment of metrology marks may fail to properly align layers due to distortion of metrology marks from chemical mechanical polishing, optical shifting from light refraction, and poor observability from shallow metrology marks, low transmissivity or high transmissivity (especially with planarized layers). Similarly, topology metrology marks may fail to be properly align layers due to distortion of metrology marks from chemical mechanical polishing, physical shifting of the topology of topological metrology marks by uneven removal and/or distortion of metrology marks from chemical mechanical polishing.
Accordingly, there is a strong need in the art for an alignment technique that overcomes the aforementioned problems.
An aspect of the present invention is to provide an alignment method including detecting a topology of at least one layer, determining an apparent location of a metrology mark, adjusting the apparent location of the metrology mark to determine an adjusted location of the metrology mark, and aligning another layer according to the adjusted location of the metrology mark.
Another aspect of the present invention is to provide a fabrication method for a layered device including providing a substrate including a metrology feature, determining the topology of one or more layers formed on the substrate, forming a patterned layer on the one or more layers formed on the substrate, determining whether the patterned layer is within one or more tolerances, the one or more tolerances being determined in accordance with the topology of the one or more layers, and selecting the next processing step in accordance with whether the patterned layer is within the one or more tolerances.
Another aspect of the present invention is to provide an apparatus for aligning including a detector for detecting a topology of at least one layer to determine an apparent location of a metrology mark, the apparent location of the metrology mark being offset from the actual position of the metrology mark by a distortion amount, and a mask which is aligned according to the apparent location and adjustment information, wherein the adjustment information is corresponds to the distortion amount.
Another aspect of the present invention is to provide a layered device including a plurality of patterned layers, at least one of the plurality of patterned layers being planarized and having at least one topological metrology feature indicative of a position of a pattern of another of the plurality of patterned layers, and an aligned layer aligned with the pattern of the another of the plurality of patterned layers which includes an alignment adjustment to compensate for the at least one of the plurality of patterned layers being planarized.
Another aspect of the present invention is to provide a layered device including a plurality of patterned layers, at least one of the plurality of patterned layers being planarized and having a metrology feature indicative of a position of a pattern of another of the plurality of patterned layers, and a masking layer aligned with the pattern of the another of the plurality of patterned layers which includes an alignment adjustment to compensate for the at least one of the plurality of patterned layers being planarized.
To the accomplishment of the forgoing and related ends, the invention, then, comprises the features herein after fully described and particulary pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.